First demonstration of fully standardized chiplets, supporting O(m^n) system permutations (m=library size, n=substrate sockets).
Active 3D silicon substrates that decouple compute and networking, enabling a standardized "building blocks" approach to system composition.
Sub 0.1 pj/bit chiplet communication efficiency.
Cambridge, MA – Jun 22, 2026 – Zero ASIC, a company on a mission to democratize silicon through chiplets and design automation, today announces general availability of the Platypus Z1015 12nm eFPGA IP core. Platypus addresses a long standing critical issue of FPGA obsolescence and vendor lock that has put critical infrastructure at risk.
Cambridge, MA – June 9, 2026 – Zero ASIC, a U.S. semiconductor startup on a mission to democratize silicon, today announced the release of PackageCompilerTM, the world's first truly autonomous chip package compiler.
At Zero ASIC our mission is to revolutionize silicon system design. If you are looking to really make a difference, you should considering joining us. There is no other company in the industry quite like it!
Today Zero ASIC announces the release of a new set of breakthrough open standard eFPGA cores with an advanced set of embedded BRAM and DSPs.
Cambridge, MA – September 17, 2025 – Zero ASIC, a U.S. semiconductor startup on a mission to democratize silicon, today announced the release of WildebeestTM, the world's highest performance open source FPGA synthesis tool. Wildebeest is the first open source logic synthesis solution with Quality of Results (QoR) comparable to proprietary vendor locked tools.
Today Zero ASIC is announcing availability of a production-grade, open-source static timing analysis (STA) flow for FPGAs, enabling analysis of complex multi-clock designs for the open-source FPGA design community.
