Platypus Embedded FPGAs

Platypus^TM is a family of standardized embedded FPGA (eFPGA) IP cores.

Value Proposition

Platypus is the ONLY commercial eFPGA product backed up by:

• 100% open and standardized FPGA architectures
• 100% open source FPGA bitstream formats
• 100% open source FPGA development tools

Applications

• FPGA/CPLD/ASIC obsolescence
• hardware security
• I/O peripherals
• interface bridges
• motor control
• signal muxing
• power management
• glue logic

Open Architecture Releases

• March 18, 2025 (V0.1.0)

Product Matrix

The following table shows Platypus eFPGA IP cores currently available (RC) or in development (RM). Platypus eFPGA cores are available as licensable hard IP. (RC=release candidate, RM=roadmap)

Part Number	Status	LUTs	DSPs	BRAM	I/O	Clocks
Z1000-GF12LP	RC	2,048	0	0	1,024	4
Z1002-GF12LP	RM	8,192	0	0	2,048	4
Z1004-GF12LP	RM	32,768	0	0	4,096	4
Z1008-GF12LP	RM	131,072	0	0	8,192	4
Z1010-GF12LP	RM	TBD	TBD	TBD	TBD	4

All Platypus eFPGA hardened IP cores are backed up by an open architecture guarantee. Complete machine readable descriptions of standard architectures can be found in the Logiklib open source repository.

Parametrized soft RTL logic wrap the hardened IP core to handle reset, boot-up, security, and bitstream loading. Bitstream programming is done via a standardize memory mapped register interfaces (APB, AXI-Lite, or UMI) selectable by the user during design integration.

Z1000-GF12LP

The Z1000 standard eFPGA architecture has been ported to the GlobalFoundries GF12LP process. The picture below shows the full layout (GDS) of an integration ready Z1000 eFPGA core.

Process	LUTs	Regs	I/O	DSPs	BRAM	Width	Height
GF12LP	2,048	2,048	1,024	0	0	1036.8um	1037.2um

Z1010-GF12LP-BETA

An experimental Z1010 heterogeneous eFPGA architecture with LUTs, DSPs, and BRAMs has been ported to the GlobalFoundries GF12LP process. The picture below shows the full layout of the experimental architecture. The official Z1010 standard will include a different ratio of LUTs, DSPs, and BRAM.

Process	LUTs	Regs	I/O	DSPs	BRAM	Width	Height
GF12LP	512	512	1,024	16	1Mb	1036.8um	1037.2um

Development Tools

Platypus device programming is done via Logik, an open source fully automated RTL-to-bits SiliconCompiler based toolchain that that seamlessly integrates a complete set of industrial strength open source source FPGA development tools. The Logik FPGA tool chain includes support for:

• High level design languages: SystemVerilog, Verilog, VHDL, C, Chisel, Python, Bluespec
• Logic Simulation: Verilator, Icarus, GHDL
• Synthesis: Yosys
• Placement and Routing: VPR
• Bitstream Generation: FASM
• Build Automation: SiliconCompiler
• IP Package Management: SiliconCompiler

Demo

To evaluate the Platypus eFPGA cores Logik development tools, download the open source Logik repository and run the ethernet MAC example as shown below. The example demonstrates 100% automated compilation of RTL code into a bitstream for the Z1000 eFPGA. To fully appreciate the elegance of the Logik development tools, we recommend reviewing the simple 60 line Python run script “eth_mac_1g.py”.

git clone https://github.com/siliconcompiler/logik
cd logik
pip install -e .[test]
cd examples/eth_mac_1g
python eth_mac_1g.py

IP Deliverables

Front-end views

Deliverables for evaluation, system design, simulation and chip floor-planning.

Deliverable	File format
Datasheet	PDF, HTML
Integration Guide	PDF, HTML
Footprint	LEF
Timing model	Liberty
Timing constraints	SDC
Testbench	Verilog
Wrapper RTL	Verilog

Back-end views

Deliverables for sign-off level verification and chip tapeout.

Deliverable	Format
Netlist	Verilog, Spice
Parasitics	SPEF
Layout	DEF, GDSII
Layer map	CSV

Access Model

Platypus eFPGA cores are available via commercial IP agreements. Contact our team to find out more about licensing terms and availability.