Who We Are

A diverse and talented chip design team on a mission to reduce the cost and time of ASIC design by 100X.

Core Technology

• Active interposers
• Embedded FPGA generator
• Application class RISC-V CPU
• AI accelerator (2-20 TOPS)
• Network-On-Chip
• Silicon Compiler
• Digital Twin System Emulator

• Billions of unique System-In-Package assembly options
• 512 Gbps/mm on-fabric bisection bandwidth
• 128 Gbps/mm chiplet 2D bandwidth
• 128 Gbps/mm2 chiplet 3D bandwidth
• <0.1 pJ/bit 3D interconnect energy efficiency

To enable plug-and-play chiplet composability, Zero ASIC has created a set of electrical and mechanical 3D chiplet interface standards and validated the standards through tapeouts of a canonical set of processing chiplets.

Zero ASIC's one of a kind Digital Twin Emulation tools allows users to test out their custom designs quickly and accurately before ordering physical devices, using cloud FPGAs to implement the RTL source code of each chiplet in a custom SoC.