Democratizing silicon.
Step 1: Emulate
Leverage Digital Twin technology to construct and test systems using off the shelf virtual chiplets.
Step 2: Prototype
Build low cost chiplet based prototypes to validate applications and end markets.
Step 3: Optimize (optional)
Optimize solution based on market feedback.
Step 4: Production
Place standard purchase orders or negotiate a production agreement.
Profit!
Zero ASIC is building the world’s first composable chiplet platform, enabling billions of unique silicon systems to be assembled in hours from a catalog of off-the-shelf chiplets.
First demonstration of fully standardized chiplets, supporting O(m^n) system permutations (m=library size, n=substrate sockets).
Active silicon substrates decouples compute and networking, enabling LEGO like system composition, scalable from low power edge AI to data-center scale HPC applications.
Sub 0.1 pj/bit chiplet communication penalty.
Our Switchboard digital twin platform supports rapid design exploration and validation before committing to time consuming and expensive hardware prototyping. The operational theory behind our approach is detailed in this scientific paper.
Our chiplet optimized digital twin platform enables an order of magnitude faster build and run times compared to leading commercial emulators.
Our latency insensitive enable wafer scale designs and beyond.
Standardized model interfaces facilitate seamless transitions between high-level models (e.g. QEMU), cycle-accurate RTL simulators (e.g. Verilator), and hardware-in-the-loop systems (e.g. AWS F1 FPGAs).
Modern EDA tools are incredibly complex, requiring large teams of experts to operate correctly. To lower the barrier to chiplet design for all, Zero ASIC developed SiliconCompiler, an open source hardware compiler platform. The principles behind SiliconCompiler are documented in this 2022 DAC paper.
Silicon proven flows supporting a large set of open source and proprietary EDA tools and PDKs.
Parametric chiplet generators and programmatic flows enable automated chip compilation.
Optimized cloud scale build infrastructure enable rapid design cycles.
Standardized manifests and design-as-code approach enable guarantee compilation determinism.
No lock in or hidden agendas!
Composable chiplets represent a powerful new design approach with the potential of disrupting a large portion of the semiconductor market. This month I will be presenting ideas for how chiplets can be applied to a number of critical applications.
Today, Zero ASIC is releasing a demo that shows how to create a custom EBRICK, a chiplet that can plug into our SiP design ecosystem. The demo can be found on GitHub.
Chiplets are all the rage these days, even making MIT Technology Review's 10 Breakthrough Technologies of 2024. This is pretty incredible for such a niche technology! Unfortunately, as of today chiplets are only accessible to semiconductor mega-corps. To unlock the true power of disaggregated chiplet innovation, we need to drastically reduce the barriers to chiplet based design.
